Why signal integrity for pcb design

Devices designed for very high data rates require logic that transitions much faster between ON and OFF states. With faster rise times comes stronger crosstalk, stronger ringing, and greater likelihood that an interconnect will behave as a transmission line.

This is where a routing strategy, impedance-controlled design, and proper layer stackup become important for ensuring your traces can resist crosstalk and EMI, as well as suppress transmission line effects.

Interconnect design strategies geared towards high speed design can ensure signal integrity and suppression of external radiated EMI in more complex systems. Interconnects in your board carry your high speed signals around your board and should be designed to suppress or eliminate common signal integrity problems. Signal integrity design considerations, specifically with respect to interconnect design, involve impedance-controlled routing, proper stackup design, length matching tolerance, and termination network design for impedance matching during high speed layout.

Overshoot and undershoot are potential signal integrity problems that can arise in high speed designs. Interconnect design is also related to layer stack design as your layer stack can provide shielding against EMI , determine the characteristic impedance of your traces, influence crosstalk between traces, and increase the chance your device will pass EMC tests.

All these issues affect signal integrity throughout your board and whether you can implement impedance-controlled routing in your PCB. With all the signal integrity problems that can arise in a high speed board, there are some important design techniques to consider during the PCB layout phase.

Instead, consider the following points when building your next high speed PCB. Your layer stack performs a number of functions in high speed design and is a significant signal integrity design consideration.

By far, the most popular design choice for ensuring signal integrity in multilayer boards with single ended traces is to route signal traces directly over a ground plane. Traces can be routed through the inner layers, but it is best to place inner signal layers between solid copper planes to prevent crosstalk and shield these traces from external EMI.

Taking advantage of shielding provided by ground planes can also help you pass EMC checks. Read more about designing your PCB stackup. The real factor that determines whether certain traces in your board should be designed as impedance-matched transmission lines is the length of an interconnect between a source and a load.

When the time required for a signal to travel along a trace is longer than approximately one-quarter of the signal rise time, then the trace can behave as a transmission line. Impedance mismatches between the source and the trace, or between the load and the trace, will cause a signal reflection. A signal reflection at the source will propagate a signal back into the IC package, but this is generally ignored in high speed design as signals reflected back into an IC are blocked thanks to the structure of transistors in the driver.

Signal reflections at a load are much more important as they can cause ringing in an underdamped trace. Ringing refers to a transient oscillation in a trace, where the transient signal oscillates at its natural frequency. This is where a series termination resistor at the load is important for perfectly damping the trace and suppressing ringing. Working with high speed clocks and signals requires precise length matching of traces throughout a group of signals within some allowable tolerance.

When signals are sent to a load component, the signals will require some specific amount of time to switch between ON and OFF. Traces carrying data in parallel need to be precisely length matched to ensure that all signals reach the load at the same time.

Similarly, traces with serial and parallel data streams must be length matched to the clock signal in order to ensure that the load IC switches at the right moment. Additionally, sufficient decoupling directly across the chip can assist with some of the related effects. This aspect of signal integrity arises from the fact that signals appearing on one line appear on nearby lines.

This can result in spurious spikes and other signal appearing on nearby lines. This can cause erroneous data or clocking pulses to appear, and these can be very difficult to track down in some circumstances. Poor signal integrity from crosstalk arises from two causes, namely mutual inductance, and mutual capacitance. The mutual inductance is the effect that is used in transformers. It arises from the fact that a current in one track sets up a magnetic field. Changes in this field then induce a current in a nearby track.

Mutual capacitive occurs as a result of the coupling of the electric fields between two tracks. A voltage appearing on one track creates an electric field which can couple to a second line. Changing voltages, especially fast edges can result in similar edges appearing on nearby lines. There are several techniques that can be used to overcome these effects. As poor signal integrity from crosstalk arises from mutual inductance and capacitance, the solutions involve taking steps to reduce them.

This can be achieved in a number of ways by arranging the layout accordingly. The routing should avoid lines that run parallel to one another. If lines have to cross, this should be achieved at right angles, and using layers as far apart as possible. Line spacing should be as wide as possible, and to reduce mutual capacitance lines should be as thin as possible.

Finally, where transmission lines are used, they should be as close to the ground plane as possible. This will reduce coupling to other nearby lines. There are a number of other ideas that can be implemented to assist maintaining good levels of signal integrity.

One area to which particular attention should be paid is the clocking circuitry. As it generates a regular clocking pulse, this can create a background noise if the signal integrity measures are not incorporated. Accordingly it is necessary to ensure that measures to reduce crosstalk on the clock lines are implemented. In particular, signal lines should be kept away from the clock lines, and they should not be routed underneath each other.

If this is necessary then the ground or earth plane should be between them. To ensure the signal integrity, it is also necessary to ensure the lines are well matched so that ringing is prevented. This can add additional spikes that may be transmitted around the circuitry. Another method of improving signal integrity is to ensure that all chips are adequately decoupled.

Poor decoupling will add to the noise present on the circuits and this may impact the signal integrity. Signal integrity of a device is ensured by designing the wires and interconnects so that they carry correct and uncorrupted data. Analog signal integrity was a challenge to design but digital systems are comparatively easier to design. Still, digital systems are also susceptible to noise.

The size of devices are reducing with technology and so the interconnects are placed close together. It is important to follow good practices and check for integrity right from the simulation stage itself. It is better to focus on signal integrity during simulation and floor planning stage, since not much can be done after physically designing the PCB. The most important issues that affect the quality of signal transmission in a PCB are transmission line effects, impedance mismatch, high-speed switching characteristics, board material loss, and crosstalk.

These issues and their remedies will be discussed in detail. Transmission lines are defined as a conductive medium or connection between the transmitter and a receiver, which is capable of carrying a signal.

At high-speed digital signal transmission, even the shortest passive printed circuit board PCB tracks are affected by the transmission line effects.

At low frequencies, the impedance of a transmission line is only resistive. Hence the characteristic impedance of the transmission line can be expressed at low frequencies as.

At high frequencies, the AC circuit characteristics become dominant in the transmission line and this is due to the introduction of capacitive and inductive reactance. The reactance is the complex part of impedance. So at high frequencies the impedance of the transmission line can be realized as. Where X L is inductive reactance which is directly proportional to frequency and X C is capacitive reactance which is indirectly proportional to frequency.

In case of any discontinuities such as open or closed circuit, the signal is lost in the form of radiation or reflection. The factors affecting the resistance and reactance of the transmission lines in PCB are line thickness, dielectric constant of the board, distance between the line and the ground plane.

So by playing around with any of these parameters the designer has to maintain the impedance same along the length of the transmission line. A similar scenario to the transmission line effects is the impedance matching. For maximum coupling of signal power between two ports, the load impedance of the output port has to the equal to the characteristic impedance or the internal impedance of the circuit.

When there is a mismatch between these impedances not all of the signal power is coupled, but a part of the signal is reflected back in the transmission line. This causes standing wave in the transmission line leading to overshoot, undershoot, stair step waveforms and ringing. These conditions affect signal integrity vastly. Impedance mismatching problems can be eliminated by careful selection of medium and by termination schemes.

The selection of termination scheme depends on the application and requirement. A simple parallel resistor to the ground simple parallel termination or a complex RC termination which is a low pass filter used to remove low frequency noise and to pass the high frequencies can be used. Stub matching is also a solution to match the impedance correctly.

Simple Parallel Termination. Choice of PCB materials affect the signal transmission. Signal losses occur due to attenuation. Dielectric material is an indispensable material in PCB. At high frequencies the molecules of the dielectric medium are excited.